This week on the IEEE Digital Elements and Packaging Know-how Convention, Intel unveiled that it’s creating new chip packaging expertise that may enable for greater processors for AI.
With Moore’s Regulation slowing down, makers of superior GPUs and different information heart chips are having so as to add extra silicon space to their merchandise to maintain up with the relentless rise of AI’s computing wants. However the most dimension of a single silicon chip is mounted at round 800 sq. millimeters (with one exception), in order that they’ve needed to flip to superior packaging applied sciences that combine a number of items of silicon in a approach that lets them act like a single chip.
Three of the improvements Intel unveiled at ECTC have been aimed toward tackling limitations in simply how a lot silicon you’ll be able to squeeze right into a single package deal and the way huge that package deal might be. They embody enhancements to the expertise Intel makes use of to hyperlink adjoining silicon dies collectively, a extra correct technique for bonding silicon to the package deal substrate, and system to increase the scale of a important a part of the package deal that take away warmth. Collectively, the applied sciences allow the mixing of greater than 10,000 sq. millimeters of silicon inside a package deal that may be greater than 21,000 mm2—an enormous space in regards to the dimension of 4 and a half bank cards.
EMIB will get a 3D improve
One of many limitations on how a lot silicon can slot in a single package deal has to do with connecting a lot of silicon dies at their edges. Utilizing an natural polymer package deal substrate to interconnect the silicon dies is essentially the most reasonably priced possibility, however a silicon substrate permits you to make extra dense connections at these edges.
Intel’s answer, launched greater than 5 years in the past, is to embed a small sliver of silicon within the natural package deal beneath the adjoining edges of the silicon dies. That sliver of silicon, referred to as EMIB, is etched with positive interconnects that enhance the density of connections past what the natural substrate can deal with.
At ECTC, Intel unveiled the newest twist on the EMIB expertise, referred to as EMIB-T. Along with the standard positive horizontal interconnects, EMIB-T offers comparatively thick vertical copper connections referred to as through-silicon vias, or TSVs. The TSVs enable energy from the circuit-board under to immediately hook up with the chips above as an alternative of getting to route across the EMIB, lowering energy misplaced by an extended journey. Moreover, EMIB-T incorporates a copper grid that acts as a floor airplane to scale back noise within the energy delivered attributable to course of cores and different circuits immediately ramping up their workloads.
“It sounds easy, however this can be a expertise that brings loads of functionality to us,” says Rahul Manepalli, vp of substrate packaging expertise at Intel. With it and the opposite applied sciences Intel described, a buyer may join silicon equal to greater than 12 full dimension silicon dies—10,000 sq. millimeters of silicon—in a single package deal utilizing 38 or extra EMIB-T bridges.
Thermal management
One other expertise Intel reported at ECTC that helps enhance the scale of packages is low-thermal-gradient thermal compression bonding. It’s a variant of the expertise used as we speak to connect silicon dies to natural substrates. Micrometer-scale bumps of solder are positioned on the substrate the place they may hook up with a silicon die. The die is then heated and pressed onto the microbumps, melting them and connecting the package deal’s interconnects to the silicon’s.
As a result of the silicon and the substrate increase at completely different charges when heated, engineers need to restrict the inter-bump distance, or pitch. Moreover, the enlargement distinction makes it troublesome to reliably make very massive substrates stuffed with a number of silicon dies, which is the route AI processors must go.
The brand new Intel tech makes the thermal enlargement mismatch extra predictable and manageable, says Manepalli. The result’s that very-large substrates might be populated with dies. Alternatively, the identical expertise can be utilized to extend the density of connections to EMIB right down to about one each 25 micrometers.
A flatter warmth spreader
These greater silicon assemblages will generate much more warmth than as we speak’s programs. So it’s important that the warmth’s pathway out of the silicon isn’t obstructed. An built-in piece of metallic referred to as a warmth spreader is essential to that, however making one sufficiently big for these massive packages is troublesome. The package deal substrate can warp and the metallic warmth spreader itself won’t keep completely flat; so it won’t contact the tops of the new dies it’s purported to be sucking the warmth from. Intel’s answer was to assemble the built-in warmth spreader in elements as an alternative of as one piece. This allowed it so as to add additional stiffening elements amongst different issues to maintain every little thing in flat and in place.
“Maintaining it flat at greater temperatures is a giant profit for reliability and yield,” says Manepalli.
Intel says the applied sciences are nonetheless within the in R&D stage and wouldn’t touch upon when these applied sciences would debut commercially. Nonetheless, they may doubtless need to arrive within the subsequent few years for the Intel Foundry to compete with TSMC’s deliberate packaging enlargement.
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